This invention relates generally to methods of operating memory cells and more particularly to methods of operating semiconductor memory cells for use in associative memories.
In the prior art, associative semiconductor memories have been developed, but the size and power consumption of the memory cells utilized in such memories have made them uneconomical and has limited the size of such memories that can be economically fabricated on a single semiconductor chip.
The basic operation of an associative memory, the search for a match between a given word and the words stored in the memory, can be implemented with software and non-associative memories used to store the data. Therefore a viable semiconductor memory cell for use in associative memories must compare favorably with the semiconductor memory cells currently used in random access memories, and in particular with dynamic semiconductor memory cells such as the one transistor memory cell. The memory cells used in prior art associative memories have usually been of the static or quasi-static type in which cross-coupled circuit elements such as field effect transistors (FETs) are used to form the storage element. It is well known in the semiconductor arts, that such static memory cells consume considerably more power than do dynamic semiconductor memory cells. Also such static memory cells require considerably more circuit elements and therefore require considerably more semiconductor surface area per stored bit than do dynamic semiconductor memory cells. A problem with using dynamic semiconductor memory cells in associative memories is that in the prior art, the methods of determining the datum stored in a memory cell was destructive of that datum.